Wed 19:01:24: Loaded debugee: E:\Projects\TSMs\TMPM350\Blinking_LED\Debug iFlash\Exe\Blinking_LED.out Wed 19:01:24: 1532 bytes downloaded into FLASH and verified (0.81 Kbytes/sec) Wed 19:01:24: Hardware reset with strategy 3 was performed Wed 19:01:24: SYSRESETREQ has confused core. Wed 19:01:23: Core did not halt after reset, trying to disable WDT. Wed 19:01:23: Found Cortex-M3 r2p0, Little endian.
Iar arm kickstart code#
Wed 19:01:23: FPUnit: 6 code (BP) slots and 2 literal slots Wed 19:01:22: Downloaded E:\Projects\TSMs\TMPM350\Blinking_LED\Debug iFlash\Exe\Blinking_LED.out to flash memory. Wed 19:01:22: Loaded debugee: D:\IAR_Systems\Embedded_Workbench_6.0_Kickstart\arm\config\flashloader\Toshiba\ Wed 19:01:22: 1480 bytes downloaded and verified (11.56 Kbytes/sec) Wed 19:01:22: Executing execUserFlashInit() function Wed 19:01:22: Initial reset was performed Wed 19:01:22: Hardware reset with strategy 3 was performed Wed 19:01:22: SYSRESETREQ has confused core. Wed 19:01:20: Core did not halt after reset, trying to disable WDT. Wed 19:01:19: Found Cortex-M3 r2p0, Little endian. Wed 19:01:19: FPUnit: 6 code (BP) slots and 2 literal slots Wed 19:01:19: JTAG speed is initially set to: 32 kHz Wed 19:01:19: Selecting SWD as current target interface. Wed 19:01:19: JLINK command: device = TMPM350FDTFG, return = 0 Wed 19:01:19: JLINK command: ProjectFile = E:\Projects\TSMs\TMPM350\Blinking_LED\settings\Blinking_LED_Debug iFlash.jlink, Wed 19:01:19: Logging to file: E:\Projects\TSMs\TMPM350\Blinking_LED\cspycomm.log Wed 19:01:18: Loaded macro file: D:\IAR_Systems\Embedded_Workbench_6.0_Kickstart\arm\config\flashloader\Toshiba\ I played a "little bit" with Reset Option (J-Link/J-Trace Setup Tab).Īfter switching Reset to "Connect during reset" the failure is gone. Info: Found Cortex-M3 r2p0, Little endian. Info: FPUnit: 6 code (BP) slots and 2 literal slots Info: TotalIRLen = ?, IRPrint = 0x.FFFFFFFFFFFFFFFFFFFFFFF1
SEGGER J-Link Commander V4.40b ('?' for help)įirmware: J-Link ARM V8 compiled 18:57:44 > Could you please post the output of J-Link Commander? > Is J-Link able to halt the CPU using the "h" command? > Is J-Link still able to connect to the device?
Iar arm kickstart software#
> The simplest way would be to download the latest version of the J-Link software and documentation package (V4.40b, /jlink-software.html) > As a first try, you should check if basic communication with the device using J-Link is still working. Tue 09:45:11: Failed to load flash loader: D:\IAR_Systems\Embedded_Workbench_6.0_Kickstart\arm\config\flashloader\Toshiba\FlashTMPM350FDTFG.flash Tue 09:45:11: Failed to load flash loader: D:\IAR_Systems\Embedded_Workbench_6.0_Kickstart\arm\config\flashloader\Toshiba\FlashTMPM350FDTFG.out Tue 09:45:11: Fatal error: Failed to read CPUID for Cortex device Session aborted! Tue 09:44:46: Initial reset was performed Tue 09:44:46: Hardware reset with strategy 1 was performed Tue 09:44:46: JTAG speed is initially set to: 32 kHz Tue 09:44:46: Selecting SWD as current target interface. Tue 09:44:46: JLINK command: device = TMPM350FDTFG, return = 0 Tue 09:44:46: JLINK command: ProjectFile = E:\System\Documents\_TMPM350\Blinking_LED\settings\Blinking_LED_Debug iFlash.jlink, return = 0
Tue 09:44:46: Logging to file: E:\System\Documents\_TMPM350\Blinking_LED\cspycomm.log Tue 09:44:46: Loaded macro file: D:\IAR_Systems\Embedded_Workbench_6.0_Kickstart\arm\config\flashloader\Toshiba\FlashTMPM350FDTFG.mac * Here is the Debug Log from IAR Workbench IDE: I use TMPM350-SK (IAR KickStart Kit) evaluation board. RAM is successful (Debug iRAM configuration), download to flash is therefore failed. When i put the board into "boot mode" via J3P1 (MODE0), J3P2(MODE1) only the download to The same failure is occured with "Debug iFlash" configuration is in use. Retry?" after this i can only abort the current session (see appended log output). Program, so i get "J_link Dialog" with "Failed to get CPU status after 4 I have trouble with J-Link used from "IAR Workbench IDE".
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